1. Field of the Invention
The present invention relates generally to semiconductor device manufacturing. More particularly, the present invention relates to a method for fabricating a metal-oxide-semiconductor (MOS) transistor having a gate structure and embedded SiGe.
2. Description of the Prior Art
As known in the art, strained silicon technologies have been introduced in the MOS manufacturing process in order to increase the mobility of electrons or holes, thereby attaining higher performance of a semiconductor device. For example, taking advantage of the lattice constant of SiGe layer being different from that of Si, a strain occurs in the silicon layer growing on the SiGe layer. Since SiGe has a larger lattice constant than Si, the band structure of Si is altered, thereby increasing the mobility of the carriers.
FIG. 1 and FIG. 2 shows a prior art method for fabricating a MOS transistor utilizing embedded SiGe (e-SiGe). As shown in FIG. 1, a first spacer 21 is formed on each sidewall of the gate 10. A lightly doped drain (LDD) implant is then carried out. A disposable silicon nitride spacer 22, which is formed by using hexachlorodisilane (HCD) precursor, is formed. Subsequently, recess 31 is formed by etching the substrate 1 in the source/drain region adjacent to the gate 10. Thereafter, as shown in FIG. 2, a pre-clean is carried out prior to the epitaxial growth, for example, to remove any native oxide from the substrate 1 and the recess 31 by using diluted HF (DHF). A SiGe forming process is then performed to form the embedded SiGe layer 42 in the recess 31. The SiGe forming process may comprise pre-bake, Si seed layer deposition, SiGe epitaxial growth and silicon cap formation.
However, one problem associated with the above-described prior art method is that corner rounding of the embedded SiGe layer 42 occurs in the lower corners of the recess 31, as specifically indicated by label 46. In FIG. 2, the original contour of the recess 31 is drawn in dashed line. This corner rounding phenomenon leads to disordered silicon channel between source and drain and therefore longer source to drain channel distance, which results in device performance. One approach to solving this corner rounding problem is to lower the temperature during pre-bake process, which is typically controlled at below 750° C., for example, 720° C. On the other hand, this approach is problematic because the lower pre-bake temperatures degrade the ION current of the transistor device.
Therefore, a need exists for an improved method for forming a semiconductor device such as a metal-oxide-semiconductor (MOS) transistor having a gate structure and embedded SiGe, which allows a higher pre-bake temperature, for example, 800° C., for improved manufacturability and yield.